1. Field of the Invention
The present invention relates to a dynamic RAM (DRAM) comprising a plurality of memory cells each constituted by a MOS capacitor and a MOSFET and a method of manufacturing the same.
2. Description of the Related Art
A high packing density and a large capacity of a MOS DRAM have progressed by micropatterning of elements. A DRAM structure suitable for a high packing density and a large capacity is disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056. In this DRAM, grooves are formed in longitudinal and transverse directions in a semiconductor substrate. Semiconductor pillar projections are arranged in memory cell regions, respectively. A MOS capacitor is formed on side surfaces at a lower portion of each pillar projection, and a MOSFET is formed on side surfaces at an upper portion thereof. In the DRAM structure disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056, a bottom portion of each groove serves as an element isolating region, and the MOS capacitor and the MOSFET are vertically stacked in the groove. Therefore, since an area occupied by a memory cell can be decreased, a high packing density can be obtained.
In the DRAM structure disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056, however, a bit line is connected to an n-type layer formed on an upper end face of the pillar projection via a contact hole. For this reason, the size of the upper end face of each pillar projection is defined in accordance with a degree of an alignment margin between the bit line contact hole and the upper end face of the pillar projection. Therefore, even if a minimum design rule is used, an area of the upper end face of the pillar projection cannot be a minimum patterning size.
In addition, in order to form the MOS capacitor, an n-type layer which is one electrode of the capacitor and serves as a memory node is desirably formed in the semiconductor layer. In the DRAM structure disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056, however, formation of this n-type layer is difficult because the capacitor must be formed on the side surfaces at the lower portion of the pillar projection before a gate electrode of the MOSFET is formed. In order to selectively dope an impurity in the side surfaces of a capacitor region, a MOSFET formation region must be covered with some kind of a mask. After formation of the grooves, however, it is difficult to adopt such a manufacturing step.
Recently, one of most serious problems in a DRAM is a soft error phenomenon. In the soft error phenomenon, a storage state in a memory cell changes upon incidence of rays, and an error occurs.
Since each memory cell is formed on the side surfaces of the pillar projection, rays which are obliquely incident are interrupted by an array of the pillar projections. As a result, a soft error in a cell mode is reduced. Since no insulating film is present right just below the pillar projections, however, rays incident from right just above cannot be suppressed. Therefore, a soft error must be reduced.
In the DRAM structure disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056, however, an insulating layer is buried in the bottom portion of each pillar projection. It is difficult to manufacture a DRAM by this method. That is, in order to isolate adjacent MOS capacitors, an element isolating insulating film is formed on the bottom of the groove, but it is very difficult to bury such an insulating film on the bottom of a narrow groove having a high aspect ratio.
In addition, in the DRAM structure disclosed in Japanese Patent Disclosure (Kokai) No. 60-152056, a gate electrode material remains on a side wall of a step present at an end portion of a memory cell array. Since a step is also present on a groove formation portion, the gate electrode material remains on the side wall of the step when it is subjected to anisotropic etching (RIE). Each word line is short-circuited due to the residual gate electrode material.
In order to solve this problem, a method of etching and removing the gate electrode material remaining in a region between adjacent word lines by using conventional photolithography has been proposed.
An interval between the adjacent word lines, however, is minimum. Therefore, it is difficult to form an etching window considering an alignment margin in the region between the adjacent word lines.
As a result, the size of a memory cell is increased.